TI SN74LS112AN - Dual J−K Negative Edge Triggered Flip−Flop TTL IC, NOS

Description

TI SN74LS112AN - Dual J−K Negative Edge Triggered Flip−Flop With Preset And Clear TTL IC, NOS
The SN74LS112AN contains two independent J−K negative−edge−triggered flip−flops in a 16−Lead plastic DIP type package. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative−going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. This versatile flip−flop can perform as a toggle flip−flop by tying J and K high.
* Supply Voltage: 7V
* Max Input Current: 1mA
* Equal to NTE74LS112A
* Sold as
2
pieces per lot
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