1/5/10Pcs TI SN74S112AN Dual J-K Neg. Edge-Triggered Flip Flop w/ Preset, Clear

Description

1/5/10Pcs TI SN74S112AN Dual J-K Neg. Edge-Triggered Flip Flop w/ Preset, Clear
These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset and clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and dear are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.
SPECIFICATIONS
Manufacturer: Texas Instruments
Part Number: SN74S112AN
Product Category: Flip Flops
Number of Circuits: 2
Logic Family: S
Logic Type: J-K Type Flip-Flop
Polarity: Inverting/Non-Inverting
Input Type: TTL
Output Type: TTL
Propagation Delay Time: 7 ns
High Level Output Current: - 1 mA
Low Level Output Current: 20 mA
Supply Voltage - Min: 4.75 V
Supply Voltage - Max: 5.25 V
Minimum Operating Temperature: 0 C
Maximum Operating Temperature: + 70 C
Mounting Style: Through Hole
Package / Case: PDIP-16
Function: JK Type
Height: 4.57 mm
Length: 19.3 mm
Operating Temperature Range: 0 C to + 70 C
Width: 6.35 mm
Number of Channels: 2
Number of Input Lines: 5
Number of Output Lines: 2
Operating Supply Voltage: 4.75 V to 5.25 V
Reset Type: Set, Reset
Subcategory: Logic ICs
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